A 12.5 mW, 11.1 $text/sqrt}$, −115 dB THD, $ < 1 mutext$ Settling, 18 bit SAR ADC Driver in 0.6 $mutext$ CMOS

PROJECT TITLE :

A 12.5 mW, 11.1 $text/sqrt}$, −115 dB THD, $ < 1 mutext$ Settling, 18 bit SAR ADC Driver in 0.6 $mutext$ CMOS

ABSTRACT:

A driver amplifier appropriate for integration with an 18 bit five hundred kS/s successive approximation register analog-to-digital converter (ADC) is reported. It accepts single-ended or fully differential inputs. The driver consumes 12.five mW from a 5 V offer, contains a −115 dB (−one hundred twenty dB) total harmonic distortion for 8 Vppd output at 1 kHz (ten kHz), a 240 ns settling time to zero.01% accuracy for a two Vppd output step, and an input-referred noise of eleven.1 $textnV/sqrttextHz$. Simulated eighteen bit settling time is 90zero ns, and $3sigma$ input-referred offset is 1.a pair of mV. This is one of the first reported 18 bit CMOS ADC driver amplifiers, and its performance is adore that of the state-of-the-art parts in different processes.

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